Because present trends in designing microelectronic devices and circuits are toward increased miniaturization, higher component density and greater number of component leads per piece-part, there is a corresponding need for connectors that can be configured in high-density, large-number arrays. Techniques known in the art for providing high-density interconnections between an integrated circuit (IC) or multi-chip module (MCM) and a printed wiring board (PWB) include using a quad flat-pack (QFP) which surrounds an integrated circuit (IC) or multi-chip module (MCM) on four sides with wire/lead interconnections, and using a leadless chip-carrier (LCC) which surrounds the four outer planes of an IC/MCM with vertical, flush, interconnecting leads. High-density interconnection techniques wherein connections are arranged in a two-dimensional array located under or near the substrate of an IC/MCM or the base of a PWB include the use of land grid arrays (LGA""s), ball grid arrays (BGA""s), and pin grid arrays (PGA""s). LGA""s and BGA""s have become popular in part arrays (PGA""s). LGA""s and BGA""s have become popular in part because production equipment used to mount and solder surface-mount devices onto circuit boards can be easily adapted. This ease of manufacture is enhanced by the tendency of BGAs during soldering to self-align because of the effects of surface tension caused from the molten solder.
Chip-scale packaging is another emerging technique for interfacing an IC to a substrate/circuit board. Still in its infancy, this technology has the potential to cost-effectively provide direct connections between package or circuit board input/output (I/O) pads to IC die or MCM substrates.
Because circuit miniaturization and high-density components entail ever-increasing signal speeds and input/output rates, newly developed devices increasingly require interconnections that can provide adequate shielding and maintain a proper and uniform characteristic impedance. These properties are particularly necessary to pass low-noise signals or signals with fast edges (xcex94v/xcex94t). In PWB design, characteristic impedance control has been achieved by using strip-line or micro-strip techniques which requires careful control of the size, position and spacing of circuit traces within a dielectric away from a ground or reference plane. However, applying strip-line or micro-strip connections to the inner pads of a high-density PWB becomes more difficult as circuit density increases. Also, more layers and increased manufacturing must be used when a device includes numerous, high-density, shielded and/or impedance-controlled interconnections. Increased circuit density requires more connections per unit area, especially if numerous ground planes (as required when using micro-strips or strip-lines) are utilized.
The need to interconnect to electronic components and their receptacles with impedance-controlled transmission lines is increasing with increasing clock speeds and as the density of electronic devices increase. If the impedances between the output impedance, transmission line and input impedance are not uniform, then reflections are created that decreases signal integrity and increases electromagnetic interference (EMI).
In addition, there is an increased need to integrate as many support functions in with the electronic devices to enable higher integration. Such functions include series dampening resistors and parallel loading.
U.S. Pat. No. 4,679,321 to J. P. Plonski describes an interconnection board for high frequency signals wherein connectors are in close proximity. The board is constructed having one side provided with a ground plane and the other side provided with terminal pads and interconnection conductors. Holes are drilled through the board at the terminal points. An end of the center conductor of a coaxial cable, stripped of insulation, is inserted through each hole while the conductive shield remains on the other side of the board. Each bare-wire conductor is connected to a pad and the conductors are scribed and bonded into place. The shields can be interconnected by applying a plated copper layer or a conductive encapsulating layer or by reflow soldering.
U.S. Pat. No. 3,114,194 to W. Lohs describes a method of wiring an electrical circuit upon an insulating plate provided with a plurality of holes, whereby wire lengths are kept as short as possible and wires can be crossed. Insulated wire is drawn through a hole in the plate and a loop formed from the wire projecting through the hole. The loop is then crushed to simultaneously anchor the loop into the hole and expose a conductive area.
U.S. Pat. No. 5,042,146 (""146) by the present inventor, discloses a process and apparatus for forming double-helix contact receptacles directly from insulated wire for interconnecting components independent of printed circuitry. Some of the apparatus disclosed therein, specifically the wire processing mechanism including cutting, stripping, and handling assemblies, is readily adaptable to the present invention which, like the ""146 patent, is capable of handling and incorporating both single and twisted-pair insulated wire. Alternatively, coaxial cable can be used with the center conductor in lieu of a single conductor, provided the shield does not contact the center conductor.
U.S. Pat. No. 5,250,759 (""759), also by the present inventor, for SURFACE MOUNT COMPONENT PADS, is incorporated herein by reference in its entirety; ""759 discloses a method to form pads for surface-mount electronic components by inserting a stripped portion of insulated wire into an elongated rectangular opening, and anchoring the U-shaped loop thus formed into place with epoxy or a plug. Although the pads disclosed in the ""759 patents can be used with area arrays, their elongated pads will not mesh well geometrically with the square pads normally used in arrays. In addition, due to their shape, elongated pads cannot be disposed sufficiently dense in planar arrays to meet the close proximity requirements of LGA""s or BGA""s.
U.S. Pat. No. 5,755,596, also by the present inventor, for a HIGH-DENSITY COMPRESSION CONNECTOR, is also incorporated herein by reference in its entirety, discloses a method to form contact receptacles for high-density area arrays and connectors from sections of insulated wire. In this patent a stripped section of insulated wire is formed into a short loop, this loop inserted into an insulating sleeve, and this insulating sleeve is inserted into a receptacle of a housing.
U.S. Pat. No. 6,010,342 entitled SLEEVELESS HIGH-DENSITY COMPRESSION CONNECTOR, a continuation-in-part of ""596, where the insulation portion of insulated wire takes the place of the insulating sleeve. Both the ""596 and ""342 patents use wire segments or loops as the central conductive elements but do not provide for the incorporation of resistive elements.
U.S. patent application Ser. No. 09/406,471 entitled xe2x80x9cHIGH-DENSITY COMPRESSION CONNECTOR WITH RESISTIVE OPTIONxe2x80x9d filed Sep. 27, 1999 describes a pin-type compression connector that details an optional resistive element that is placed in series with the connection. The issue of characteristic impedance is discussed as a goal in this application but details on how the characteristic impedance can be varied is not discussed.
It is a primary object of the present invention to provide a mechanically rugged multiple connector assembly with capability to incorporate a controlled amount of series resistance and resistance to ground.
It is a another object of the present invention to provide a multi-unit connector assembly allowing limited control of the characteristic impedance of each signal in a high-density connector array.
Another object is to provide an ability to interconnect electronic circuit and cable assemblies by means of compression of one contact element to another.
A further object is to provide a multiple connector capable of providing shielding between all elements of the connector array.
Another object is to provide a multi-unit connector that is simple to manufacture and repair.
Another object is to achieve high density and ability to interconnect to contemporary microelectronic circuits and devices such as interconnect pads of surface-mount, area-arrayed electronic devices including ball-grid arrays, land-grid array, chip-scale or flip-chip packages.
Yet another object is to provide a multi-unit connector that is reliable and easy to use.
These and other objects are achieved by the present invention, a compression-contact connector assembly implemented as a plurality of cylindrical electrically conducting elements mounted in an array of cylindrical through-openings in a housing panel. The housing panel can be electrically conductive to serve as a ground reference (or other electrical reference), to provide a path for parallel loading, and/or to facilitate the shielding of orthogonal electrostatic forces. The housing panel can also be magnetically permeable to allow the conduction of magnetic lines of force, thereby facilitating H-field shielding. The electrically conductive element has one end configured to attach to a bared portions of interconnection wire on one side of the housing panel and the opposite end configured as a contact surface. The electrically conductive elements can be made highly conductive or can be made to have a specified resistance value. For the purpose of this disclosure, the term resistance is defined as any electrical resistance greater than 0.1 ohm, the term electrically conductive is defined as any electrical resistance less than 0.1 ohm. In particular, reference to resistive within these parameters is intended to refer to the use of a component as a resistor rather than a conductor, that is, adding resistance that ordinarily would not exist in a component. The attachment end can be made in several alternative configurations directed to coaxial or flat ribbon type interconnection wire in either unshielded or shielded versions. The contact end can be made in various shapes: e.g. planar, concave to engage solder balls, convex, or pointed to penetrate non-conductive coatings. The contact ends in an array can be kept aligned in a plane by an attached annular flange surrounding each conducting element near the contact end.